Cross-String Current Sharing

When several battery strings are connected in parallel — for instance, a number of series-built modules joined at a common DC bus bar — it is tempting to assume the pack current divides evenly between them. In practice it almost never does. Small differences in interconnect resistance, cell-to-cell variation in state of health (SoH), and drift in state of charge (SoC) between strings all cause current to split unevenly. This is cross-string current sharing, and left unmanaged it can quietly overload the healthiest-looking string in a pack while another sits underused.

Why Strings Never Share Current Perfectly

Several effects combine to unbalance current between strings, and they don’t need to be large individually to matter:

Interconnect and bus bar resistance — physical path length from each string to the common bus, joint/contact resistance from torque or weld quality variation, and busbar cross-section all differ slightly string to string.
Cell manufacturing tolerance — even cells from the same production batch have a spread in internal resistance and capacity, which shows up as string-to-string SoH divergence as the pack ages.
Thermal gradients across the pack change local impedance, since internal resistance is temperature-dependent — a string near a cooling inlet behaves differently to one in a warmer corner.
SoC drift between strings, from unequal self-discharge or imperfect balancing, shifts each string’s open-circuit voltage (OCV) relative to the others.

A Simple Circuit Model

Each string can be modelled as a Thevenin source: an open-circuit voltage set by its SoC, in series with a lumped internal resistance covering both the cells and their interconnects. All strings are tied to the same bus voltage. For string i, the current it contributes is:

Schematic of three battery strings, each modelled as an open-circuit voltage source in series with a resistance, connected in parallel to a common DC bus bar feeding a load — Each string as a Thevenin source (OCV in series with R), all tied to the same bus.

I_i = \\frac{V_{OCV,i} – V_{bus}}{R_i}

with the constraint that the individual string currents sum to the total pack current being drawn:

\\sum_i I_i = I_{total}

Two things fall out of this immediately: if every string shares the same OCV, current divides in inverse proportion to resistance (the lowest-resistance string takes the most current). If resistances are matched but OCVs differ, the strings with higher OCV push current into the ones with lower OCV even before any external load is applied — and once a load is applied, that circulating tendency adds to (or subtracts from) each string’s share of the load current.

Worked Example 1: Resistance Mismatch Only

Consider three strings in parallel at a DC block, all at the same SoC (so equal OCV), supplying a combined discharge current of 300 A. Interconnect and contact resistance differences give each string a slightly different total resistance: R₁ = 48 mΩ, R₂ = 50 mΩ, R₃ = 55 mΩ — a spread of under 15% between the tightest and loosest string. Because the OCVs are equal, current divides in inverse proportion to resistance:

String 1 (48 mΩ): 105.9 A
String 2 (50 mΩ): 101.7 A
String 3 (55 mΩ): 92.4 A

A 15% resistance spread produces roughly a 13% spread in current between the busiest and quietest string — noticeable, but modest next to what a small SoC mismatch does.

Worked Example 2: Same Resistance Spread, Plus a Small SoC Mismatch

Keep the same three resistances, but now let string 3 sit about 2% lower in SoC than strings 1 and 2 — easily within what imperfect balancing leaves behind. For a 100s string that might mean an OCV of 367 V for string 3 against 370 V for strings 1 and 2, a gap of under 1%. Solving the circuit for the same 300 A total load now gives a common bus voltage of about 364 V, and:

String 1 (48 mΩ, 370 V OCV): ≈125 A
String 2 (50 mΩ, 370 V OCV): ≈120 A
String 3 (55 mΩ, 367 V OCV): ≈55 A

A SoC gap of roughly 2% has done far more damage to the current split than the resistance mismatch on its own: string 3’s contribution drops by around 41%, while strings 1 and 2 pick up the slack, ending up 20–25% above their “fair share” of 100 A. The lesson generalises — because OCV differences act directly against comparatively small string resistances, even a small SoC mismatch tends to dominate over realistic resistance mismatches as a source of current imbalance.

That comparison is only valid because Example 2 changed one thing at a time: the resistances are identical to Example 1, so the entire swing between the two examples — strings 1 and 2 gaining roughly 19 A each, string 3 losing roughly 38 A — is attributable to the added OCV/SoC mismatch on its own, not tangled up with the resistance term. Because string current is a linear function of both resistance and OCV for a fixed total load, the two effects add: resistance mismatch alone pulled string 3 about 7.6 A below its 100 A fair share (Example 1); layering the SoC mismatch on top pulled it a further ~38 A below that (Example 2) — roughly five times the resistance-driven effect on its own. That is what “the SoC gap did more damage” actually means here: not just a bigger final number, but a larger isolated contribution once resistance is held constant.

Grouped bar chart comparing string currents in Example 1 (resistance mismatch only: 105.9, 101.7, 92.4 A) versus Example 2 (resistance plus small SoC mismatch: 125, 120, 55 A), against a 100 A fair-share reference line — Same resistance spread in both examples — the extra spread in Example 2 is attributable to the added SoC/OCV mismatch.

Why It Matters

The overloaded strings run at a higher effective C-rate, dissipate more I²R heat, and age faster — while the underloaded string barely contributes to delivering pack power despite being just as capable, effectively hiding usable capacity. Over many cycles this can become self-reinforcing: strings that run hotter and harder tend to lose capacity and gain resistance faster, widening the very mismatch that overloaded them in the first place.

Connection Geometry: Bus Bar Layout Matters

The resistance term above isn’t purely random — physical busbar layout sets a systematic component of it. Daisy-chaining a busbar from one end bakes in a resistance gradient that grows with distance from the feed; center-feeding, star wiring, closing the bus into a ring, and grading its cross-section to the current it carries each remove or flatten that gradient to a different degree, at a different cost in copper and complexity. See Busbar Layout for Parallel Strings for the resistance math behind each option.

Managing It

Minimise resistance mismatch: symmetric or center-fed bus bar layout rather than daisy-chaining, consistent joint torque/weld quality, and cell binning by internal resistance at build.
Minimise SoC mismatch: cell binning by capacity and SoH at build, periodic top-balancing, and — for architectures where string imbalance is severe or safety-critical — independent string-level control such as per-string contactors or DC-DC stages rather than relying on passive parallel connection alone.
Monitor at string level: pack-level SoC and current readings average away exactly the mismatch that matters here, so detecting a developing imbalance requires string-level current (and ideally temperature) sensing, not just pack-level totals.