Hybrid Pulse Power Characterisation for Battery Cells
Overview
HPPC (Hybrid Pulse Power Characterisation) maps a cell’s dynamic power capability and direct current internal resistance (DCIR) across its usable SoC range by applying paired discharge and charge current pulses at each SoC step. The resulting resistance profile versus SoC and temperature feeds directly into BMS current limit estimation, State of Power (SoP) estimation, and equivalent circuit model (ECM) parameterisation.
The test originated in the USABC/PNGV development programme and remains the most widely used cell-level resistance characterisation technique in automotive battery engineering. It is used at initial cell qualification, as a reference performance check during ageing studies, and as a source of BMS calibration data.
Purpose
- Derive discharge and charge DCIR at each SoC step and test temperature
- Generate the SoC and temperature-dependent resistance lookup tables used by the BMS for current limit estimation
- Provide input data for ECM parameterisation (R0, R1, C1 in a first-order Thevenin model)
- Track resistance growth during ageing programmes as part of a Reference Performance Test (RPT)
- Characterise maximum discharge capability as a function of SoC and temperature
Pre-conditions
- Cell must have completed a minimum of three formation cycles before HPPC characterisation
- Fully charge the cell using the manufacturer CC/CV profile; rest at open circuit for 1 h minimum before beginning the sequence
- Four-wire Kelvin connections are required at the cell tabs; see Four-Wire (Kelvin) Resistance Measurement for connection practice. Two-wire connections introduce contact resistance errors that inflate the measured R0 at short pulse durations
- Thermal chamber must be at target temperature and the cell must be thermally soaked for at least 2 h before the first pulse. For large-format prismatic or cylindrical cells, 3 h is advisable
- Cycler channel must support constant current within +/-1% of the demanded value and log voltage at minimum 100 ms resolution
Pulse Current Rate
The standard base protocol uses a 1C discharge pulse and a 0.75C charge pulse. In practice, automotive programmes frequently characterise at higher C-rates to capture the behaviour relevant to peak power events. Common options are:
- 1C discharge / 0.75C charge: baseline characterisation, lowest self-heating, suitable for reference datasets
- 2C discharge / 1.5C charge: typical automotive cell qualification; better captures resistance at driving-relevant pulse amplitudes
- 3C discharge / 2C charge: high-power cell characterisation; may require active cooling between SoC steps to maintain temperature stability
Where resources allow, running two C-rate variants (e.g. 1C and 3C) at 25°C reveals the degree of rate-dependent polarisation in the cell and improves ECM accuracy at the extremes of the power map.
Always confirm with the cycler manufacturer that the hardware can sustain the demanded current to the target cell voltage without derating. Some cyclers reduce current as terminal voltage approaches the limit.
Test Sequence
The procedure steps down from the top of the usable SoC range to the lower voltage limit in 10% SoC decrements. At each level the sequence is: step-down, rest, discharge pulse, short rest, charge pulse, rest.
| Step | Action | Detail | Notes |
| 1 | Condition cell | CC/CV charge to Vmax at C/5; rest 1 h OCV | Skip if cell was charged in previous 24 h and rested 1 h |
| 2 | Thermal soak | Set chamber to target temperature; hold until cell core is at setpoint (min. 2 h for large-format cells) | Monitor surface thermocouple; allow additional soak if surface-to-target delta > 1°C |
| 3 | Step to first SoC | CC discharge at C/3; remove Ah to reach 90% SoC by Coulomb counting from rated capacity | Do not use voltage as SoC target |
| 4 | Rest | Open circuit; hold for 1 h minimum | LFP cells may need 2 h at extreme SoC; monitor OCV drift rate |
| 5 | Discharge pulse | Apply 1C for 10 s; record V at t = 0 s and t = 10 s; record I | Capture at 100 ms resolution minimum; log 1 s sample within pulse for R0/R1 separation |
| 6 | Rest | Open circuit; 40 s | Sufficient for ohmic recovery; polarisation will not fully relax in this window |
| 7 | Charge pulse | Apply 0.75C for 10 s; record V at t = 0 s and t = 10 s; record I | Charge pulse is asymmetric to avoid Coulomb imbalance across the SoC sweep |
| 8 | Rest | Open circuit; 1 h minimum before next SoC step | Critical: this is the inter-step rest, not the post-pulse rest in step 6 |
| 9 | Repeat | Repeat steps 3 to 8 at SoC = 80%, 70%, 60%, 50%, 40%, 30%, 20%, 10% | Nine SoC levels total; each requires its own rest and pulse pair |
DCIR Calculation
Discharge resistance at each SoC point:
R_discharge = (V_pre – V_10s) / I_discharge
Charge resistance at each SoC point:
R_charge = (V_10s – V_pre) / I_charge
Where V_pre is the open-circuit voltage recorded at the start of the pulse (t = 0 s) and V_10s is the terminal voltage at end of the 10 s pulse. Pulse current I is taken as positive for discharge by convention.
The 10 s pulse duration captures ohmic resistance plus the fast electrochemical polarisation contribution. A 1 s sample logged within the pulse allows separation of the purely ohmic R0 component from the polarisation term R1 in Thevenin ECM fitting. The 1 s DCIR value is approximately equal to R0; the 10 s value gives R0 + R1.
See Internal Resistance: DCIR and ACIR for a comparison of DCIR measurement methods and the relationship between DCIR and ACIR (EIS-derived) values.
Temperature Matrix
A single-temperature dataset at 25°C is sufficient for initial resistance screening. Full BMS calibration requires a minimum of three temperatures to support Arrhenius interpolation. Standard automotive characterisation covers:
| Temperature | Application | Notes |
| -20°C | Cold start / crank limit | Longest soak time; NMC charge pulse may be disabled below 0°C |
| 0°C | Winter driving baseline | Resistance typically 2-3x higher than at 25°C |
| 25°C | Reference temperature | Normalisation point for ageing comparisons and ECM parameterisation |
| 45°C | Hot climate / thermal management limit | Upper bound for most EV operating conditions |
Allow full thermal soak between temperature setpoints. The cell must reach thermal equilibrium through its core, not only at the surface thermocouple. This is particularly important for large-format cylindrical cells (46xx format) and thick prismatic cells where core-to-surface gradients can exceed 5°C after the C/3 step-down.
Outputs
- DCIR vs SoC curves at discharge and charge for each test temperature
- OCV vs SoC curve (derived from pre-pulse rest voltages at each SoC step)
- ECM parameters: R0, R1, C1 at each SoC and temperature (requires additional fitting step to a first-order Thevenin equivalent circuit model)
- Peak power capability map: P_discharge and P_charge vs SoC and temperature, derived from DCIR and cell voltage limits
- Inputs for BMS algorithms: resistance lookup tables for SoC, SoH, and temperature-corrected current limiting
Common Measurement Errors
| Error | Cause | How to avoid |
| Elevated pre-pulse voltage | Insufficient rest after C/3 step-down | Hold 1 h OCV minimum; verify OCV drift rate < 1 mV/min before applying pulse |
| SoC targeting error | Voltage used instead of Coulomb counting | Track Ah removed from verified full-charge baseline; reset at each temperature |
| Temperature gradient error | Core temperature lags surface thermocouple | Extend soak time for large-format cells; use embedded thermocouple where possible |
| R0 inflation | Poor Kelvin contact at cell tabs | Measure contact resistance at zero current before and after test sequence |
| Coulomb imbalance | Symmetric charge and discharge pulses | Use asymmetric pulse ratio (e.g. 10 s / 0.75C charge vs 10 s / 1C discharge) |
Use in Ageing Programmes
HPPC is routinely inserted as a Reference Performance Test (RPT) checkpoint during calendar and cycle ageing studies. A typical RPT sequence is:
- C/5 capacity check
- HPPC resistance check (1C at 25°C, selected SoC points only if test time is constrained)
- EIS sweep at reference SoC (see Electrochemical Impedance Spectroscopy)
- Slow-rate OCV measurement (C/20 or lower)
HPPC resistance growth tracked against cycle count or calendar time provides the resistance fade component of the SoH model. A 30% increase in R_discharge at 50% SoC and 25°C is a common end-of-life threshold in automotive applications, alongside capacity fade to 80% of initial.
Standards and References
- USABC Electric Vehicle Battery Test Procedures Manual (Rev. 2) – defines the original HPPC protocol and pulse current selection rationale
- FreedomCAR Battery Test Manual for Power-Assist Hybrid Electric Vehicles – extends the protocol for high-power applications
- IEC 62660-1 – secondary lithium-ion cells for propulsion; performance testing framework including resistance characterisation
- ISO 12405-4 – lithium-ion traction battery packs and systems; references HPPC-derived characterisation for system-level power capability
Related Pages
DCIR of a Cell | Internal Resistance: DCIR and ACIR | Equivalent Circuit Model | Electrochemical Impedance Spectroscopy
State of Power | Current Limit Estimation | BMS Algorithms | Maximum Cell Discharge Capability